Cut and paste this URL to share the unmodified register and value:
https://regviz.com/r/Microchip Technology/ATSAME51J19A/RAMECC/INTENSET#0x0
Interrupt Enable Set
Single Bit ECC Error Interrupt Enable Set
Dual Bit ECC Error Interrupt Enable Set
https://github.com/cmsis-svd/cmsis-svd-data